1. Field of the Invention
The present invention relates to a method of satisfying an ASIC manufacturer's output toggle test requirements in an efficient, standardized manner which is not dependent on the specific primary functionality of that ASIC.
2. Description of the Related Art
A well-known method for testing complex integrated circuitry implemented within, for example, an integrated circuit (IC) chip, is the IEEE 1149.1 boundary-scan standard originated by the International Joint Test Action Group (JTAG), hereby incorporated by reference. One implementation of this standard involves designing components (e.g., integrated circuits) for serial boundary-scan testing by providing shift-register elements daisy chained to form a path around the periphery of an integrated circuit component.
The general concept for serial testing using JTAG is to shift serial data into and through a number of integrated circuit components to stimulate the circuitry therein or to generate predefined output signals from the circuitry. Thereafter, data generated by the integrated circuit components or received on inputs of the integrated circuit components are shifted from the integrated circuit components to a JTAG master testing circuit.
If the data stream returned to the master testing circuit is not as expected, then a malfunction in the circuit is detected by the testing circuit. A careful analysis under software control of the deviations in the data stream may isolate any malfunctions within a circuit.
Most application-specific integrated circuit (ASIC) vendors require that all output pins (i.e., output only pins as well as bidirectional (I/O) pins) of an IC under test be toggled within the first few hundred test vectors as part of the manufacturing test of an IC. That is, the IC testing circuit must observe a transition from a low voltage to a high voltage, as well as a transition from a high voltage to a low voltage at each output pin. This is to ensure that each of the outputs are operating properly and are capable of transitioning from state-to-state.
However, because many of the ICs tested could have complex state machine circuitry normally controlling the output pins to be toggled, complex analysis may be required to ensure that the appropriate test vectors are created cause each and every output pin to be toggled within the first few hundred test vectors. Toggling the outputs using the standard JTAG is not time-efficient for large pin count ICs since each new vector must be serially loaded through the JTAG interface. It is desirable to provide a standard method of toggling the outputs of an ASIC, or like IC, which does not depend upon the particular circuitry within the IC. Thus, a need exists for a simple and elegant method for insuring that each of the output pins on an IC is toggled.